Nanoelectronic mixed-signal system design /

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Bibliographic Details
Main Author:	Mohanty, Saraju P. (Author)
Format:	Book
Language:	English
Published:	New York : McGraw-Hill Education, [2015]
Subjects:	Nanoelectronics. Mixed signal circuits.

Table of Contents:

Machine generated contents note: 1.1. Introduction
1.2. Mixed-Signal Circuits and Systems
1.2.1. Different Processors: Electrical to Mechanical
1.2.2. Analog versus Digital Processors
1.2.3. Analog, Digital, Mixed-Signal Circuits and Systems
1.2.4. Two Types of Mixed-Signal Systems
1.3. Nanoscale CMOS Circuit Technology
1.3.1. Developmental Trend
1.3.2. Nanoscale CMOS Alternative Device Options
1.3.3. Advantages and Disadvantages of Technology Scaling
1.3.4. Challenges in Nanoscale Design
1.4. Power Consumption and Leakage Dissipation Issues in AMS-SoCs
1.4.1. Power Consumption in Various Components in AMS-SoCs
1.4.2. Power and Leakage Trend in Nanoscale Technology
1.4.3. The Impact of Power Consumption and Leakage Dissipation
1.5. Parasitics Issue
1.5.1. Types of Parasitics
1.5.2. The Impact of Parasitics
1.5.3. Challenges to Account Parasitics during Design
1.6. Nanoscale Circuit Process Variation Issues
1.6.1. Types of Process Variation
1.6.2. The Impact of Process Variation
1.7. The Temperature Variation Issue
1.7.1. The Issue of Temperature
1.7.2. The Impact of Temperature
1.7.3. Challenges to Account through PVT-Aware Design
1.8. Challenges in Nanoscale CMOS AMS-SoC Design
1.8.1. AMS-SoC Design Flow
1.8.2. AMS-SoC Unified Optimization
1.9. Tools for Mixed-Signal Circuit Design
1.9.1. The AMS-SoC Design Issue
1.9.2. Languages for AMS-SoC Design
1.9.3. Tools for AMS-SoC Design and Simulation
1.9.4. Transistor Models
1.10. Questions
1.11. References
2.1. Introduction
2.2. Atomic Force Microscope
2.2.1. What Is It?
2.2.2. Background
2.2.3. What Is Inside?
2.3. Biosensor Systems
2.3.1. What Is It?
2.3.2. Background
2.3.3. What Is Inside?
2.4. Blu-Ray Player
2.4.1. What Is It?
2.4.2. Home Video Systems Background: From Video Cassette Player to Blu-Ray Player
2.4.3. What Is Inside?
2.5. Drug-Delivery Nano-Electro-Mechanical Systems
2.5.1. What Is It?
2.5.2. Background
2.5.3. What Is Inside?
2.6. Digital Video Recorder
2.6.1. What Is It?
2.6.2. Background
2.6.3. What Is Inside?
2.7. Electroencephalogram System
2.7.1. What Is It?
2.7.2. Background
2.7.3. What Is Inside?
2.8. GPS Navigation Device
2.8.1. What Is It?
2.8.2. Background
2.8.3. What Is Inside?
2.9. GPU-CPU Hybrid System
2.9.1. What Is It?
2.9.2. Background
2.9.3. What Is Inside?
2.10. Networked Media Tank
2.10.1. What Is It?
2.10.2. Background
2.10.3. What Is Inside?
2.11. Net-Centric Multimedia Processor
2.11.1. What Is It?
2.11.2. Background
2.11.3. What Is Inside?
2.12. Radiation Detection System
2.12.1. What Is It?
2.12.2. Background
2.12.3. What Is Inside?
2.13. Radio Frequency Identification Chip
2.13.1. What Is It?
2.13.2. Background
2.13.3. What Is Inside?
2.14. Secure Digital Camera
2.14.1. What Is It?
2.14.2. Background
2.14.3. What Is Inside?
2.15. Set-Top Box
2.15.1. What Is It?
2.15.2. Background
2.15.3. What Is Inside?
3.10.1. Hot Carrier Injection
3.10.2. Negative Bias Temperature Instability
3.10.3. Latchup Effect
3.10.4. Time-Dependent Dielectric Breakdown
3.10.5. Electromigration
3.10.6. Thermal Stress
3.11. The Trust Issue
3.11.1. Information Protection Issue
3.11.2. Information Leakage Issue
3.11.3. Chip Intellectual Property Protection Issue
3.11.4. Malicious Design Modifications Issue
3.12. Questions
3.13. References
4.1. Introduction
4.2. Phase-Locked Loop System Types
4.3. Phase-Locked Loop System: A Broad Overview
4.3.1. Definition
4.3.2. Block-Level Representation
4.3.3. Characteristics, or Performance Metrics
4.3.4. Theory in Brief
4.4. Oscillator Circuits
4.4.1. Oscillator Types
4.4.2. Oscillator Characteristics, or Performance Metrics
4.4.3. Comparison of Oscillators
4.5. Ring Oscillators
4.5.1. Basics
4.5.2. 45-nm CMOS
4.5.3. Multigate FET
4.5.4. Carbon Nanotube
4.6. Current-Starved Voltage Controlled Oscillators
4.6.1. Basics
4.6.2. Circuit Design
4.6.3. 90-nm CMOS
4.6.4. 50-nm CMOS
4.6.5. 45-nm CMOS
4.6.6. 45-nm Double-Gate FinFET
4.7. LC-Tank Voltage-Controlled Oscillator
4.7.1. Basics
4.7.2. 180-nm CMOS
4.7.3. CNTFET
4.7.4. Memristor
4.8. Relaxation Oscillators
4.8.1. Low-Power Relaxation Oscillator
4.8.2. Memristor Relaxation Oscillator
4.8.3. Memristor-Based Schmitt Trigger Oscillator
4.9. Phase-Frequency Detectors
4.9.1. D Flip-Flop-Based PFD
4.9.2. XOR Gate-Based PFD
4.10. Charge Pumps
4.10.1. Basics
4.10.2. 180-nm CMOS
4.11. Loop Filters
4.12. Frequency Dividers
4.12.1. Basics
4.12.2. DFF-Based 180-nm CMOS
4.12.3. JK Flip-Flop-Based 45-nm CMOS
4.13. Design and Characterization of a 180-nm CMOS PLL
4.14. All Digital Phase-Locked Loop
4.14.1. Basics
4.14.2. A Simple ADPLL Using an NCO
4.14.3. A High-Resolution ADPLL Using Double DCO
4.15. Delay-Locked Loop
4.15.1. Basics
4.15.2. An Analog DLL for Variable Frequency Generation
4.15.3. A Digital DLL
4.16. Questions
4.17. References
5.1. Introduction
5.2. Types of Electronic Signal Converters
5.2.1. Concrete Applications
5.2.2. Signal Converter Types
5.3. Selected ADC Architectures: Brief Overview
5.3.1. Overview
5.3.2. Ramp-Compare ADC or Ramp Run-Up ADC
5.3.3. Flash ADC or Direct Conversion ADC
5.3.4. Successive-Approximation ADC
5.3.5. Integrating ADC
5.3.6. Pipeline ADC or Subranging ADC
5.3.7. Sigma-Delta ADC or Oversampling ADC
5.3.8. Time-Interleaved ADC
5.3.9. Folding ADC
5.3.10. Tracking ADC or Counter-Ramp ADC or Delta-Encoded ADC
5.3.11. Architecture Selection
5.4. Selected DAC Architectures: Brief Overview
5.4.1. Binary-Weighted DAC
5.4.2. Thermometer-Coded DAC
5.4.3. Pulse-Width Modulator DAC
5.4.4. R-2R Ladder DAC
5.4.5. Segmented DAC
5.4.6. Oversampling or Interpolating DAC
5.4.7. Sigma-Delta DAC
5.4.8. Successive-Approximation or Cyclic or Algorithmic DAC
5.4.9. Multiplying DAC
5.4.10. Pipeline DAC
5.5. Characteristics for Data Converters
5.5.1. Characteristics for ADC
5.5.2. Characteristics for DAC
5.6. A 90-nm CMOS-Based Flash ADC
5.6.1. Comparator Bank
5.6.2. 1 of N Code Generator
5.6.3. NOR ROM
5.6.4. Physical Design and Characterization of 90-nm ADC
5.6.5. Post-Layout Simulation and Characterization
5.7. A 45-nm CMOS-Based Flash ADC
5.7.1. Comparator Bank
5.7.2. 1 of N Code Generator
5.7.3. NOR ROM
5.7.4. Functional Simulation and Characterization
5.8. Single-Electron-Based ADC
5.8.1. Single-Electron Circuitry-Based ADC
5.8.2. Single-Electron Transistor-Based ADC
5.9. Organic Thin-Film Transistor-Based ADCs
5.9.1. Organic Thin-Film Transistor VCO-Based ADC
5.9.2. Complementary Organic Thin-Film Transistor-Based Successive-Approximation ADC
5.10. Sigma-Delta Modulator-Based ADC
6.6.2. Characteristics of the Image Sensors
6.6.3. A Concrete Example: 32-nm CMOS APS Design
6.6.4. Smart Image Sensors
6.6.5. Secure Image Sensors
6.7. Nanoelectronics-Based Gas Sensors
6.7.1. CNTFET-Based Gas Sensor
6.7.2. CNTFET-Based Chemical Sensor
6.8. Body Sensors
6.9. Epileptic Seizure Sensors
6.10. Humidity Sensors
6.10.1. A Diode-Based Humidity Sensor
6.10.2. A CMOS Device[
]Based Humidity Sensor
6.11. Motion Sensors
6.12. Sense Amplifiers
6.12.1. Types of Sense Amplifiers
6.12.2. Performance Metrics for the Sense Amplifiers
6.12.3. A Concrete Example: 45-nm CMOS Clamped Bitline Sense Amplifier
6.13. Questions
6.14. References
7.1. Introduction
7.2. Static Random-Access Memory
7.2.1. SRAM Array
7.2.2. Different Types of SRAM
7.2.3. Traditional Six-Transistor SRAM
7.2.4. Four-Transistor SRAM
7.2.5. Five-Transistor SRAM
7.2.6. Seven-Transistor SRAM
7.2.7. Eight-Transistor SRAM
7.2.8. Nine-Transistor SRAM
7.2.9. Ten-Transistor SRAM
7.2.10. Performance Metrics of SRAM
7.2.11. Characterization of Specific SRAMs
7.3. Dynamic Random-Access Memory
7.3.1. DRAM Array
7.3.2. Different Types of DRAM
7.3.3. Selected DRAM Designs Based on Topology
7.3.4. DRAMs Based on Modes of Operation
7.3.5. Synchronous DRAMs
7.3.6. Video or Graphics DRAM
7.3.7. Ferroelectric DRAM
7.3.8. Characteristics of DRAM
7.4. Twin-Transistor Random-Access Memory
7.5. Thyristor Random-Access Memory
7.6. Read-Only Memory
7.6.1. Programmable Read-Only Memory
7.6.2. Erasable Programmable Read-Only Memory
7.6.3. Electrically Erasable Programmable Read-Only Memory
7.7. Flash Memory
7.8. Resistive Random-Access Memory
7.8.1. Nonvolatile Resistive RAM for Storage
7.8.2. Conductive Metal-Oxide Memory
7.8.3. Memristor-Based Nonvolatile SRAM
7.9. Magnetic or Magnetoresistive Random-Access Memory
7.10. Phase-Change RAM
7.11. Questions
7.12. References
8.1. Introduction
8.2. AMS-SoC: A Complete Design Perspective
8.3. Integrated Circuit Design Flow: Top-Down versus Bottom-Up
8.4. Analog Circuit Design Flow
8.4.1. Behavioral Simulation
8.4.2. Transistor-Level Design or Schematic Capture
8.4.3. Transistor-Level Simulation and Characterization
8.4.4. Physical Design or Layout Design
8.4.5. Design Rule Check
8.4.6. Parasitic (RCLK) Extraction
8.4.7. Layout versus Schematic Verification
8.4.8. Electrical Rule Check
8.4.9. Physical Design Characterization
8.4.10. Variability Analysis
8.4.11. Performance Optimization
8.5. Digital Circuit Design Flow
8.5.1. System-Level Design
8.5.2. Architecture-Level Design
8.5.3. Logic-Level Design
8.5.4. Transistor-Level Design
8.5.5. Physical Design
8.5.6. Physical Verification
8.5.7. Design Signoff
8.5.8. Engineering Change Order
8.5.9. Circuit Fabrication, Packaging, and Testing
8.6. Analog and Mixed-Signal Circuit Design Flow
8.6.1. Mixed-Signal Design Flow
8.6.2. Analog and/or Mixed-Signal Circuit Synthesis Techniques
8.7. Design Flow Using Commercial Electronic Design Automation Tools
8.7.1. Selected Commercial EDA Tools
8.7.2. For Analog Design
8.7.3. For Digital Design
8.7.4. For Mixed-Signal System Design
8.8. Design Flow Using Free or Open-Source EDA Tools
8.8.1. Selected Free or Open-Source EDA Tools
8.8.2. For Analog Design
8.8.3. For Digital Design
8.8.4. For Mixed-Signal Design
8.9. Comprehensive Design Flows
8.9.1. For Analog/Mixed-Signal Circuits and Systems
8.9.2. For Digital Circuits and Systems
8.10. Process Design Kit and Libraries
8.11. EDA Tool Installation
8.11.1. Client-Server Platform
8.11.2. Workstation-Based Platform
8.11.3. Mixed-Configuration Platform
8.12. Questions
8.13. References
9.1. Introduction
9.2. Simulation Types and Languages for Circuits and Systems
9.2.1. Simulations Based on Abstraction Levels
9.2.2. Simulations Based on Signal Types
9.2.3. Simulations Based on System Models
9.2.4. Simulations Based on Design Tasks
9.2.5. Simulation Languages
9.3. Behavioral Simulation using MATLAB®
9.3.1. System- or Architecture-Level Simulations
9.3.2. Circuit-Level Simulations
9.3.3. Device-Level Simulations
9.4. Simulink®- or Simscape®-Based Simulations
9.4.1. System- or Architecture-Level Simulations
9.4.2. Circuit-Level Simulations
9.4.3. Device-Level Simulations
9.5. Circuit-Level and/or Device-Level Analog Simulations
9.5.1. SPICE Analog Simulation Background
9.5.2. Commercial Accurate Analog Circuit Simulators
9.5.3. Free and/or Open-Source Accurate SPICE
9.5.4. Fast SPICE
9.5.5. Analog-Fast SPICE
9.5.6. High-Speed SPICE
9.5.7. Different Types of Analysis using SPICE
9.5.8. SPICE-Based Simulation Examples
9.5.9. Inside of SPICE
9.5.10. SPICE Simulation Flow
9.6. Verilog-A-Based Analog Simulation
9.6.1. Verilog-A-Based Circuit-Level Simulations
9.6.2. Verilog-A-Based Device-Level Simulations
9.7. Simulations of Digital Circuits or Systems
9.7.1. SystemVerilog-Based Simulation
9.7.2. VHDL-Based Simulation
9.7.3. MyHDL-Based Simulation
9.7.4. SystemC-Based Simulation
9.8. Mixed-Signal HDL-Based Simulation
9.8.1. Verilog-AMS-Based Simulation
10.3.3. Digital SoC Power or Energy Optimization Procedures: An Overview
10.4. Presilicon Power Reduction Techniques
10.4.1. Brief Discussion
10.4.2. Dual-Threshold-Based Circuit-Level Optimization of a Universal Level Converter
10.4.3. Dual-Oxide-Based Logic-Level Optimization of Digital Circuits
10.4.4. Dual-Oxide-Based RTL Optimization of Digital Circuits
10.5. Hardware-Based Postsilicon Power Reduction Techniques
10.5.1. Brief Discussion
10.5.2. Dynamic or Variable Frequency Clocking for Power Reduction
10.5.3. Adaptive Voltage Scaling for Power and Energy Reduction
10.6. Dynamic Power Reduction Techniques
10.6.1. Brief Discussion
10.6.2. Dual-Voltage and Dual-Frequency-Based Circuit-Level Technique
10.6.3. Multiple Supply Voltage-Based RTL Technique
10.7. Subthreshold Leakage Reduction Techniques
10.7.1. Brief Discussion
10.7.2. Dual-Threshold-Based Circuit-Level Optimization of Nano-CMOS SRAM
10.8. Gate-Oxide Leakage Reduction Techniques
10.8.1. Brief Discussion
10.8.2. Dual-Oxide-Based Circuit-Level Optimization of a Current-Starved VCO
10.8.3. Dual-Oxide-Based RTL Optimization of Digital ICs
10.9. Parasitics: Brief Overview
10.10. The Effects of Parasitics on Integrated Circuits
10.10.1. Parasitics in Real-Life Example Circuits
10.10.2. Effects of the Parasitics
10.11. Modeling and Extraction of Parasitics
10.11.1. Signal Propagation: In a Real Wire
10.11.2. Parasitics Modeling and Simulation: The Key Aspects
10.11.3. Circuit (Device+Parasitic) Extraction Process
10.11.4. Parasitics Extraction Techniques
10.11.5. Parasitics Modeling
10.11.6. Parasitics Model Order Reduction
10.12. Design Flows for Parasitic-Aware Circuit Optimization
10.12.1. Parasitic-Aware Analog Design Flow with Multilevel Optimizations
10.16.1. Hardware-Based Thermal Monitoring
10.16.2. Software-Based Temperature Monitoring
10.16.3. Hybrid Hardware- and Software-Based Thermal Monitoring
10.17. Temperature Control or Management
10.17.1. Basic Principle
10.17.2. Types
10.18. Thermal-Aware Circuit Optimization
10.18.1. A Thermal-Aware SRAM Optimization
10.18.2. A Thermal-Aware VCO Optimization
10.19. Thermal-Aware Digital Design Flows
10.19.1. Thermal-Aware Digital Synthesis
10.19.2. Thermal-Aware Physical Design
10.20. Thermal-Aware Register-Transfer-Level Optimization
10.21. Thermal-Aware System-Level Design
10.22. Questions
10.23. References
11.1. Introduction
11.2. Methods for Variability Analysis
11.2.1. Monte Carlo Method
11.2.2. Design of Experiments Method
11.2.3. Corner-Based Method
11.2.4. Fast Monte Carlo Methods
11.3. Tool Setup for Statistical Analysis
11.4. Methods for Variability-Aware Design Optimization
11.4.1. Brief Concept
11.4.2. Variability-Aware Schematic Design Optimization Flow
11.4.3. Single Manual Layout Iteration Automatic Flow for Variability-Aware Optimization
11.5. Variability-Aware Design of Active Pixel Sensor
11.5.1. Impact of Variability on APS Performance Metrics
11.5.2. Variability-Aware APS Optimization
11.6. Variability-Aware Design of Nanoscale VCO Circuits
11.6.1. A Conjugate-Gradient-Based Optimization of a 90-nm CMOS Current-Starved VCO
11.6.2. A Particle Swarm Optimization Approach for a 90-nm Current-Starved VCO
11.6.3. Process Variation Tolerant LC-VCO Design
11.7. Variability-Aware Design of the SRAM
11.8. Register-Transfer-Level Methods for Variability-Aware Digital Circuits
11.8.1. Brief Overview
11.8.2. A Simulated-Annealing-Based Statistical Approach for RTL Optimization
11.8.3. A Taylor-Series Expansions Diagram-Based Approach for RTL Optimization
11.8.4. Variability-Aware RTL Timing Optimization
11.8.5. RTL Postsilicon Techniques for Variability Tolerance
11.9. System-Level Methods for Variability-Aware Digital Design
11.10. An Adaptive Body Bias Method for Dynamic Process Variation Compensation
11.11. Parametric Variation Effect Mitigation in Clock Networks
11.12. Statistical Methods for Yield Analysis
11.13. Questions
11.14. References
12.1. Introduction
12.2. Metamodel: An Overview
12.2.1. Concept
12.2.2. Types
12.2.3. Generation Flow
12.2.4. Metamodel versus Macromodel
12.3. Metamodel-Based Ultrafast Design Flow
12.4. Polynomial-Based Metamodeling
12.4.1. Theory
12.4.2. Generation
12.4.3. Ring Oscillator
12.4.4. LC-VCO
12.4.5. Verilog-AMS Integrated with Polynomial Metamodel for an OP-AMP
12.4.6. Verilog-AMS Integrated with Polynomial Metamodel for a Memristor Oscillator
12.4.7. Verilog-AMS Integrated with Parasitic-Aware Metamodel
12.5. Kriging-Based Metamodeling
12.5.1. Theory
12.5.2. Generation
12.5.3. Simple Kriging Metamodeling of a Clamped Bitline Sense Amplifier
12.5.4. Ordinary Kriging Metamodeling of a Sense Amplifier
12.5.5. Universal Kriging Metamodeling of a Phase-Locked Loop
12.6. Neural Network-Based Metamodeling
12.6.1. Theory
12.6.2. Generation
12.6.3. Neural Network Metamodel of PLL Components
12.6.4. Intelligent Verilog-AMS
12.6.5. Kriging Bootstrapped Training for Neural Network Metamodeling
12.7. Ultrafast Process Variations Analysis Using Metamodels
12.7.1. Kriging-Metamodel-Based Process Variation Analysis of a PLL
12.7.2. Neural Network Metamodel-Based Process Variation Analysis of a PLL
12.7.3. Kriging-Trained Neural Network-Based Process Variation Analysis of a PLL
12.8. Polynomial-Metamodel-Based Ultrafast Design Optimization
12.8.1. Polynomial-Metamodel-Based Optimization of a Ring Oscillator
12.8.2. Polynomial-Metamodel-Based Optimization of a PLL
12.8.3. Polynomial-Metamodel-Based Optimization of an OP-AMP
12.9. Neural Network Metamodel-Based Ultrafast Design Optimization
12.9.1. Neural Network Metamodel-Based Optimization of an OP-AMP
12.9.2. Neural Network Metamodel-Based Variability-Aware Optimization of a PLL
12.10. Kriging Metamodel-Based Ultrafast Design Optimization
12.10.1. Simple Kriging Metamodel-Based Optimization of a Thermal Sensor
12.10.2. Ordinary Kriging Metamodel-Based Optimization of a Sense Amplifier
12.11. Questions
12.12. References.

Nanoelectronic mixed-signal system design /

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